1. Field of the Invention
The present invention relates to a multiplier circuit useful in a computor organ.
2. Description of the Prior Art
In the COMPUTOR ORGAN disclosed in U.S. Pat. No. 3,809,786 to Deutsch, musical tones are generated by computing in real time the amplitudes X.sub.o (qR) at successive sample points (qR) of a musical waveshape. Each sample point amplitude is obtained by individually calculating the constituent Fourier component contributions F.sup.(n) and summing these in an accumulator to obtain ##EQU1## WHERE N SPECIFIES THE Fourier component order and W is the highest order component included in the waveshape synthesis. Each Fourier component is obtained in accordance with the relationship ##EQU2## WHERE C.sub.n is a harmonic amplitude coefficient that establishes the relative amplitude of the n.sup.th order component. The value R is a frequency number that is proportional to the fundamental frequency of the generated tone, and q is an integer (q=1,2,3 . . .) that is incremented at regular time intervals t.sub.x, each time a subsequent sample point amplitude is computed.
As part of each calculation of F.sup.(n) in accordance with equation 2, a multiplication operation is performed wherein the value C.sub.n is multiplied by sin .pi./WnqR. The appropriate sin value is obtained from a sinusoid table, that is, a memory which stores values of sin .phi. over some range, say 0&lt;.phi.&lt; 2.pi., at intervals of D, where D is the resolution constant of the memory.
Advantageously each sin value is stored as a fixed point binary number S. For example, the number S may have the form EQU S=s.sub.o 2.sup.o +s.sub.1 2.sup.-.sup.1 +s.sub.2 2.sup.-.sup.2 +s.sub.3 2.sup.-.sup.3 + . . . s.sub.q 2.sup.-.sup.q (Eq. 3)
where s.sub.o,s.sub.1,s.sub.2, . . . ,s.sub.q each is a binary bit of value 0 or 1.
In the computor organ, the harmonic coefficient values C.sub.n are obtained from a set of such values stored in a harmonic coefficient memory. Because of the relatively large dynamic range of values, these coefficients C.sub.n advantageously are stored as floating point binary numbers. Such a number C may have the form EQU C=(a.sub.0 +a.sub.1 2.sup.-.sup.1 +a.sub.2 2.sup.-.sup.2 +a.sub.2 2.sup.-.sup.2 +a.sub.3 2.sup.-.sup.3 + . . . +a.sub.k 2.sup.-.sup.k)2.sup.J (Eq. 4)
where the expression within the parenthesis is mantissa of C and where J is the power to which the mantissa is raised. Each bit a.sub.0,a.sub.1,a.sub.2. . . a.sub.k in the mantissa has a value of 0 or 1. For the special case C.tbd.0 the value a.sub.o =0. For all non-zero values of C the term a.sub.o =1. The power J may have the form EQU J=(j.sub.i 2.sup.i + . . . +j.sub.3 2.sup.3 +j.sub.2 2.sup.2 +j.sub.1 2.sup.1 +j.sub.o 2.sup.o) (Eq. 5)
where each bit j.sub.o,j.sub.1,j.sub.2 . . . j.sub.i has the value 0 or 1, and where the sign of J can be either positive or negative.
Since waveshape computation in the computor organ is carried out in real time, high speed circuitry is a requirement. Conventional multiplier circuits take many clock cycles to perform each multiplication, and hence are undesirable. An object of the present invention is to provide a very fast multiplier circuit for multiplying a fixed point binary number by a floating point binary number. The fixed point multiplicand S may have the form of equation 3, or S may be greater than or equal to zero and have the form EQU S=s.sub.q 2.sup.q + . . . +s.sub.3 2.sup.3 +s.sub.2 2.sup.2 +s.sub.1 2.sup.1 +s.sub.o 2.sup.o (Eq. 6)
where each bit s.sub.o,s.sub.1,s.sub.2 . . . sq is either 0 or 1. The floating point multiplier C has the form of equation 4 with an exponent as given in equation 5 or 6.
A further object is to provide such a multiplier circuit in which the products of successive multiplications are obtained at the logic clock rate. The individual products may be delayed by a number of clock pulse times because of the logic length of the multiplier. Use of the multiplier disclosed herein is by no means limited to a computor organ. The circuit is useful in any application where some accuracy can be sacrificed in favor of obtaining the multiplication product in a very minimum of logic clock cycles.